Over the past 30 years, anti-fuse technology has attracted significant attention of many inventors, IC designers and manufacturers. An anti-fuse is a structure alterable to a conductive state, or in other words, an electronic device that changes state from not conducting to conducting. Equivalently, the binary states can be either one of high resistance and low resistance in response to electric stress, such as a programming voltage or current. There have been many attempts to develop and apply anti-fuses in microelectronic industry, but the most successful anti-fuse applications to date can be seen in FGPA devices manufactured by Actel and Quicklogic, and redundancy or option programming used in DRAM devices by Micron. Anti-fuse technology is well known in the art, and example anti-fuse transistors are shown in FIGS. 1 to 5b. 
Anti-fuse memory is one type of one-time programmable (OTP) memory in which the device can be permanently programmed (electrically) with data once. This data is programmed by an end user for a particular application. There are several types of OTP memory cells which can be used. OTP memories provide users with a level flexibility since any data can be programmed.
Anti-fuse memory can be utilized in all one time programmable applications, including RF-ID tags. RF-ID tagging applications are gaining more acceptance in the industry, particularly in sales, security, transport, logistics, and military applications for example. The simplicity and full CMOS compatibility anti-fuse memory allows for application of the RF-ID tag concept to integrated circuit manufacturing and testing processes. Therefore, IC manufacturing productivity can be increased by utilizing anti-fuse memory in combination with an RF communication interface on every wafer and/or every die on the wafer allowing for contact-less programming and reading chip specific or wafer specific information during IC manufacturing and packaging, as well as during printed circuit board assembly.
FIG. 1 is a circuit diagram illustrating the basic concept of an anti-fuse memory cell, while FIGS. 2 and 3 show the planar and cross-sectional views respectively, of the anti-fuse memory cell shown in FIG. 1. The memory cell of FIG. 1 includes a pass, or access transistor 10 for coupling a bitline BL to a bottom plate of anti-fuse device 12. A wordline WL is coupled to the gate of access transistor 10 to turn it on, and a cell plate voltage Vcp is coupled to the top plate of anti-fuse device 12 for programming anti-fuse device 12.
It can be seen from FIGS. 2 and 3 that the layout of access transistor 10 and anti-fuse device 12 is very straight-forward and simple. The gate 14 of access transistor 10 and the top plate 16 of anti-fuse device 12 are constructed with the same layer of polysilicon, which extend across active area 18. In the active area 18 underneath each polysilicon layer, is formed a thin gate oxide 20, also known as a gate dielectric, for electrically isolating the polysilicon from the active area underneath. On either side of gate 14 are diffusion regions 22 and 24, where diffusion region 24 is coupled to a bitline. Although not shown, those of skill in the art will understand that standard CMOS processing, such as sidewall spacer formation, lightly doped diffusions (LDD) and diffusion and gate silicidation, can be applied. While the classical single transistor and capacitor cell configuration is widely used, a transistor-only anti-fuse cell is further desirable due to the semiconductor array area savings that can be obtained for high-density applications. Such transistor-only anti-fuses must be reliable while simple to manufacture with a low cost CMOS process.
FIG. 4a shows a cross-sectional view of an anti-fuse transistor that can be manufactured with any standard CMOS process. Variants of this anti-fuse transistor are disclosed in commonly owned U.S. patent application Ser. No. 11/762,552, filed on Jun. 13, 2007, the contents of which are incorporated by reference. In the presently shown example, the anti-fuse transistor is almost identical to a simple thick gate oxide, or input/output MOS transistor with one floating diffusion terminal. The disclosed anti-fuse transistor, also termed a split-channel capacitor or a half-transistor, can be reliably programmed such that the fuse link between the polysilicon gate and the substrate can be predictably localized to a particular region of the device. The cross-section view of FIG. 4a is taken along the channel length of the device, which in the presently described example is a p-channel device.
Anti-fuse transistor 26 includes a variable thickness gate oxide 28 formed on the substrate channel region 30, a polysilicon gate 32, sidewall spacers 34, a field oxide region 36, a diffusion region 38 and an LDD region 40 in the diffusion region 38. A bitline contact 42 is shown to be in electrical contact with diffusion region 38. The variable thickness gate oxide 28 consists of a thick oxide and a thin gate oxide such that a portion of the channel length is covered by the thick gate oxide and the remaining portion of the channel length is covered by the thin gate oxide. Generally, the thin gate oxide is a region where oxide breakdown can occur. The thick gate oxide edge meeting diffusion region 38 on the other hand, defines an access edge where gate oxide breakdown is prevented and current between the gate 32 and diffusion region 38 is to flow for a programmed anti-fuse transistor. While the distance that the thick oxide portion extends into the channel region depends on the mask grade, the thick oxide portion is preferably formed to be at least as long as the minimum length of a high voltage transistor formed on the same chip.
In this example, the diffusion region 38 is connected to a bitline through a bitline contact 42, or other line for sensing a current from the polysilicon gate 32, and can be doped to accommodate programming voltages or currents. This diffusion region 38 is formed proximate to the thick oxide portion of the variable thickness gate oxide 28. To further protect the edge of anti-fuse transistor 26 from high voltage damage, or current leakage, a resistor protection oxide (RPO), also known as a salicide protect oxide, can be introduced during the fabrication process to further space metal particles from the edge of sidewall spacer 34. This RPO is preferably used during the salicidiation process for preventing only a portion of diffusion region 38 and a portion of polysilicon gate 32 from being salicided. It is well known that salicided transistors are known to have higher leakage and therefore lower breakdown voltage. Thus having a non-salicided diffusion region 38 will reduce leakage. Diffusion region 38 can be doped for low voltage transistors or high voltage transistors or a combination of the two resulting in same or different diffusion profiles.
A simplified plan view of the anti-fuse transistor 26 is shown in FIG. 4b. Bitline contact 42 can be used as a visual reference point to orient the plan view with the corresponding cross-sectional view of FIG. 4a. The active area 44 is the region of the device where the channel region 30 and diffusion region 38 are formed, which is defined by an OD mask during the fabrication process. The dashed outline 46 defines the areas in which the thick gate oxide is to be formed via an OD2 mask during the fabrication process. More specifically, the area enclosed by the dashed outline 46 designates the regions where thick oxide is to be formed. OD simply refers to an oxide definition mask that is used during the CMOS process for defining the regions on the substrate where the oxide is to be formed, and OD2 refers to a second oxide definition mask different than the first. Details of the CMOS process steps for fabricating anti-fuse transistor 26 will be discussed later. According to an embodiment of the present invention, the thin gate oxide area bounded by edges of the active area 44 and the rightmost edge of the OD2 mask, is minimized. In the presently shown embodiment, this area can be minimized by shifting the rightmost OD2 mask edge towards the parallel edge of active area 44. Previously mentioned U.S. patent application Ser. No. 11/762,552 describes alternate single transistor anti-fuse memory cells which can be used in a non-volatile memory array. Two transistor anti-fuse memory cells are known in the art, as shown in the example of FIGS. 5a and 5b. 
FIG. 5b shows a planar view of a two-transistor anti-fuse memory cell 48 having a minimized thin gate oxide area that can be manufactured with any standard CMOS process, according to an embodiment of the present invention. FIG. 5a shows a cross-sectional view of the memory cell 48 of FIG. 5b, taken along line B-B. Two-transistor anti-fuse memory cell 48 consists of an access transistor in series with an anti-fuse transistor. The access transistor includes a polysilicon gate 50 overlying a thick gate oxide 52, which itself is formed over the channel 54. On the left side of the channel 54 is a diffusion region 56 electrically connected to a bitline contact 58. On the right side of the channel 54 is a common diffusion region 60 shared with the anti-fuse transistor. The anti-fuse transistor includes a polysilicon gate 62 overlying a thin gate oxide 64, which itself is formed over the channel 66. Dashed outline 68 represents the OD2 mask which defines the area where thick oxide is to be formed. The thick gate oxide 52 can correspond to that used for high voltage transistors while the thin gate oxide 64 can correspond to that used for low voltage transistors. It is well known that polysilicon gates 50 and 62 can be independently controlled, or alternatively can be connected to each other as shown in FIG. 5b. In the example of FIG. 5b, both polysilicon gates 50 and 62 are part of the same polysilicon structure, and connected to a wordline through wordline contact 70. Both diffusion regions 56 and 60 can have LDD regions, which can be identically doped or differently doped, depending on the desired operating voltages to be used. Commonly owned U.S. patent application Ser. No. 11/762,552 filed on Jun. 13, 2007 describes alternate two-transistor anti-fuse memory cells which can be used in a non-volatile memory array.
The programming speed of OTP memories is relatively slow, since each programming cycle will attempt to program a certain number of data words at the same time. Following each programming cycle is a program verify cycle to ensure that the data words were successfully programmed. Any bits that do not pass the program verify step are reprogrammed. This process continues until all the memory cell states have been successfully programmed. FIG. 6a shows how an unprogrammed anti-fuse memory cell, such as anti-fuse transistor 26, is programmed. Anti-fuse transistor 26 has its gate terminal connected to a wordline WL and its single diffusion region connected to a bitline BL. Programming is effected by biasing the bitline to VSS and driving the wordline to a high voltage level VPP. VPP is selected based on the process technology and thickness of the thin gate oxide that is sufficient for forming a conductive link between the polysilicon gate and the channel region.
A successfully programmed anti-fuse transistor 26 is shown in FIG. 6b, where a conductive link 72 is formed between the polysilicon gate and the channel region. Conductive link 72 is schematically represented as a resistive connection between the wordline and the channel region under the thin gate oxide region of anti-fuse transistor 26. Therefore a programmed anti-fuse transistor having a conductive link stores one logic state of one bit of data. Accordingly, an unprogrammed anti-fuse transistor will by default store the other logic state of one bit of data. To prevent programming of the anti-fuse transistor 26, the bitline is biased to VDD while the wordline is driven to VPP. This will be sufficient for inhibiting the conductive link from forming.
Reading the anti-fuse transistor is achieved by driving the wordline to a read voltage VREAD, and by precharging the bitline to VSS, as shown in FIG. 7. If the anti-fuse transistor 26 has a conductive link 72, then the wordline will pull the bitline towards the VREAD voltage level via the conductive link 72 and the positive gate voltage of the anti-fuse transistor. This bitline voltage can be sensed and amplified by sense amplifier circuits. On the other hand, if the anti-fuse transistor 26 is not programmed, ie. does not have a conductive link 72, then the bitline will remain at approximately VSS.
Most electrically programmable non-volatile memories, such as Flash, EEPROM or anti-fuse memories, require the use of high voltages to program the memory cells. These high voltages are generated on chip and distributed to wordlines and/or bitlines during programming operations. Depending on the architecture of the memory, any number of words can be programmed simultaneously, where each word is made up of a predetermined number of bits. Assuming that the memory cells start in the unprogrammed state, logic 0 for example, only memory cells for storing a logic 1 state actually undergo programming. The number of logic 1 states to be programmed at the same time depends on the data to be programmed. Because a large number of bits may be programmed simultaneously, the finite on-chip high voltage generators may not have sufficient current to program all the selected memory cells. Hence, after a first program cycle, the cells subjected to programming must be verified to ensure that they were successfully programmed.
Verification is done by reading out the memory cells and comparing their stored logic states (logic 0 or 1) to the desired programmed state (logic 1 for example). If specific bits were not successfully programmed, as determined by the program verify cycle, then the programming cycle is repeated. However, there is no need to re-program cells which were successfully programmed. This is especially problematic for anti-fuse transistors. A programmed anti-fuse transistor has a conduction path formed between its wordline and its bitline, thus repeating a program cycle on such a cell will draw more current away from the cells where programming is still required. Hence, those memory cells must be excluded from the next programming cycle. This iterative program-verify-program sequence continues until every memory cell to be programmed has been deemed to be successfully programmed.
FIG. 8 is a block diagram of a simplified anti-fuse memory device of the prior art, illustrating the logic circuits required for implementing program verify operations. The anti-fuse memory device of FIG. 8 includes a memory array 80 consisting of anti-fuse memory cells, or other non-volatile memory cells, connected to wordlines and bitlines. Wordline drivers 82 apply the read and programming voltage levels to the wordlines, while column decoders and sense amplifiers 84 are coupled to the bitlines for sensing and multiplexing the sensed data to a data register 86. The data register 86 is primarily responsible for storing data to be programmed and for storing read data. The program-verify circuits include additional latch circuits, which can be a second data register 88, and comparison logic 90. In use program data P_DATA is received by data register 86, which is also stored in the second data register 88. Those skilled in the art will understand that other circuits required for proper operation of the memory device are intentionally omitted, in order to simplify the schematic.
Once a programming cycle has been completed, the data is read out from the memory cells being programmed, and stored in data register 86. The comparison logic 90 then compares each bit position of data registers 86 and 88 to each other. If all the bit positions match, meaning that each bit position was successfully programmed, then the status signal STATUS will have a logic level indicating that all bits were programmed. Otherwise, if just one bit position did not successfully program, then the status signal STATUS will have another logic level, indicating that at least one bit was not properly programmed. Then further program cycles are executed, while the successfully programmed bits are masked, or inhibited from further programming.
One of the main problems with this program verify scheme is that the circuit implementation consumes too much valuable circuit area. Mainly, a second data register is required for storing the program data, which will be very large if the word to be programmed is very wide. The logic required to disable successfully programmed bit positions can be complex, as can be the comparison logic used to detect the failed programming of at least one bit position. Those skilled in the art will understand that increased circuit area will directly impact the manufacturing cost of the device as more chip area is required per device.
It is, therefore, desirable to provide a program verify scheme that does not require a second data register, and can simplify program verification operations.